Bug 85947 - MMX/SSE unhandled instruction 'sfence'
Summary: MMX/SSE unhandled instruction 'sfence'
Status: RESOLVED FIXED
Alias: None
Product: valgrind
Classification: Developer tools
Component: memcheck (show other bugs)
Version: 2.1.2
Platform: Compiled Sources Linux
: NOR major
Target Milestone: ---
Assignee: Julian Seward
URL:
Keywords:
: 85948 (view as bug list)
Depends on:
Blocks:
 
Reported: 2004-07-25 16:42 UTC by Ivan Kalvachev
Modified: 2004-07-25 20:41 UTC (History)
0 users

See Also:
Latest Commit:
Version Fixed In:


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Description Ivan Kalvachev 2004-07-25 16:42:36 UTC
disInstr: unhandled instruction bytes: 0xF 0xAE 0xF8 0xF
          at 0x80CD05E: fast_memcpy_MMX2 (aclib_template.c:349)

@@ aclib_template.c:346
 #ifdef HAVE_MMX2
                 /* since movntq is weakly-ordered, a "sfence"
                  * is needed to become ordered again. */
                 __asm__ __volatile__ ("sfence":::"memory");
 #endif

I found this when tried to debuging mplayer. My processor don't have SSE support.
This 'sfence' instruction is known as MMX2 (MMXEXT, also know as integer SSE).
It is used together with movntq. I guess that memory written my movntq should
not be read before "sfence" instruction. But for now I only need not to get
error on it.
Comment 1 Tom Hughes 2004-07-25 16:52:38 UTC
Are you sure that you were using valgrind 2.1.2 here? Only as far as I can see valgrind 2.1.2 should handle that instruction just fine.
Comment 2 Ivan Kalvachev 2004-07-25 17:15:21 UTC
> ------- Additional Comments From thh cyberscience com  2004-07-25 16:52 -------
> Are you sure that you were using valgrind 2.1.2 here? Only as far as I can see valgrind 2.1.2
> should handle that instruction just fine.
> 

bash-2.05b$ valgrind --version
valgrind-2.1.2



	
		
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Comment 3 Tom Hughes 2004-07-25 17:22:48 UTC
I've just tried this (in fact I added some tests for the memory fence instructions to valgrind's test suite) and it seems to work fine for me.

I've just had a thought however - are you using an early Athlon (ie an original Athlon rather than an Athlon XP or MP)? If you're not sure that take a look at /proc/cpuinfo and see what the flags line says - if you have mmxext but not sse in the flags then that might be the problem.
Comment 4 Tom Hughes 2004-07-25 17:38:48 UTC
*** Bug 85948 has been marked as a duplicate of this bug. ***
Comment 5 Tom Hughes 2004-07-25 17:43:07 UTC
CVS commit by thughes: 

Move the decoding of SFENCE out of the SSE only part of disInstr as it
exists on Athlon's that have MMXEXT support and those don't have SSE state
so won't decode it where it was.

CCMAIL: 85947-done@bugs.kde.org


  M +19 -3     vg_to_ucode.c   1.144


--- valgrind/coregrind/vg_to_ucode.c  #1.143:1.144
@@ -3985,8 +3985,8 @@ static Addr disInstr ( UCodeBlock* cb, A
    }
 
-   /* LFENCE/MFENCE/SFENCE -- flush pending operations to memory */
+   /* LFENCE/MFENCE -- flush pending operations to memory */
    if (insn[0] == 0x0F && insn[1] == 0xAE
        && (epartIsReg(insn[2]))
-       && (gregOfRM(insn[2]) >= 5 && gregOfRM(insn[2]) <= 7))
+       && (gregOfRM(insn[2]) >= 5 && gregOfRM(insn[2]) <= 6))
    {
       vg_assert(sz == 4);
@@ -3995,5 +3995,5 @@ static Addr disInstr ( UCodeBlock* cb, A
                   Lit16, (((UShort)0x0F) << 8) | (UShort)0xAE,
                   Lit16, (UShort)insn[2] );
-      DIP("sfence\n");
+      DIP("%sfence\n", gregOfRM(insn[2]) == 5 ? "l" : "m");
       goto decode_success;
    }
@@ -6853,4 +6853,20 @@ static Addr disInstr ( UCodeBlock* cb, A
          break;
 
+      case 0xAE: /* SFENCE */
+         vg_assert(sz == 4);
+         modrm = getUChar(eip);
+         if (!epartIsReg(modrm)) {
+            goto decode_failure;
+         }
+         if (gregOfRM(modrm) != 7) {
+            goto decode_failure;
+         }
+         eip += lengthAMode(eip);
+         uInstr2(cb, SSE3, 0,  /* ignore sz for internal ops */
+                     Lit16, (((UShort)0x0F) << 8) | (UShort)0xAE,
+                     Lit16, (UShort)modrm );
+         DIP("sfence\n");
+         break;
+
       case 0x71: case 0x72: case 0x73: {
          /* (sz==4): PSLL/PSRA/PSRL mmxreg by imm8 */


Comment 6 Ivan Kalvachev 2004-07-25 17:47:00 UTC
--- Tom Hughes <thh@cyberscience.com> wrote:
> ------- You are receiving this mail because: -------
> You reported the bug, or are watching the reporter.
>       
> http://bugs.kde.org/show_bug.cgi?id=85947      
> 
> 
> 
> 
> ------- Additional Comments From thh cyberscience com  2004-07-25 17:22 -------
> I've just tried this (in fact I added some tests for the memory fence instructions to valgrind's
> test suite) and it seems to work fine for me.
> 
> I've just had a thought however - are you using an early Athlon (ie an original Athlon rather
> than an Athlon XP or MP)? If you're not sure that take a look at /proc/cpuinfo and see what the
> flags line says - if you have mmxext but not sse in the flags then that might be the problem.

Yes I do. It is 1GHz Athlon Thunderburd. And the mplayer is optimized for it.

processor       : 0
vendor_id       : AuthenticAMD
cpu family      : 6
model           : 4
model name      : AMD Athlon(tm) processor
stepping        : 2
cpu MHz         : 1000.050
cache size      : 256 KB
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 1
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov 
pat pse36 mmx fxsr syscall mmxext 3dnowext 3dnow
bogomips        : 1992.29



		
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Comment 7 Ivan Kalvachev 2004-07-25 20:41:49 UTC
Works for me.
Thank you very much.
:))

--- Tom Hughes <thh@cyberscience.com> wrote:
> ------- You are receiving this mail because: -------
> You reported the bug, or are watching the reporter.
>       
> http://bugs.kde.org/show_bug.cgi?id=85947      
> thh cyberscience com changed:
> 
>            What    |Removed                     |Added
> ----------------------------------------------------------------------------
>              Status|UNCONFIRMED                 |RESOLVED
>          Resolution|                            |FIXED
> 
> 
> 
> ------- Additional Comments From thh cyberscience com  2004-07-25 17:43 -------
> CVS commit by thughes: 
> 
> Move the decoding of SFENCE out of the SSE only part of disInstr as it
> exists on Athlon's that have MMXEXT support and those don't have SSE state
> so won't decode it where it was.
> 
> CCMAIL: 85947-done bugs kde org
> 
> 
>   M +19 -3     vg_to_ucode.c   1.144
> 
> 
> --- valgrind/coregrind/vg_to_ucode.c  #1.143:1.144
>  @ -3985,8 +3985,8  @ static Addr disInstr ( UCodeBlock* cb, A
>     }
>  
> -   /* LFENCE/MFENCE/SFENCE -- flush pending operations to memory */
> +   /* LFENCE/MFENCE -- flush pending operations to memory */
>     if (insn[0] == 0x0F && insn[1] == 0xAE
>         && (epartIsReg(insn[2]))
> -       && (gregOfRM(insn[2]) >= 5 && gregOfRM(insn[2]) <= 7))
> +       && (gregOfRM(insn[2]) >= 5 && gregOfRM(insn[2]) <= 6))
>     {
>        vg_assert(sz == 4);
>  @ -3995,5 +3995,5  @ static Addr disInstr ( UCodeBlock* cb, A
>                    Lit16, (((UShort)0x0F) << 8) | (UShort)0xAE,
>                    Lit16, (UShort)insn[2] );
> -      DIP("sfence\n");
> +      DIP("%sfence\n", gregOfRM(insn[2]) == 5 ? "l" : "m");
>        goto decode_success;
>     }
>  @ -6853,4 +6853,20  @ static Addr disInstr ( UCodeBlock* cb, A
>           break;
>  
> +      case 0xAE: /* SFENCE */
> +         vg_assert(sz == 4);
> +         modrm = getUChar(eip);
> +         if (!epartIsReg(modrm)) {
> +            goto decode_failure;
> +         }
> +         if (gregOfRM(modrm) != 7) {
> +            goto decode_failure;
> +         }
> +         eip += lengthAMode(eip);
> +         uInstr2(cb, SSE3, 0,  /* ignore sz for internal ops */
> +                     Lit16, (((UShort)0x0F) << 8) | (UShort)0xAE,
> +                     Lit16, (UShort)modrm );
> +         DIP("sfence\n");
> +         break;
> +
>        case 0x71: case 0x72: case 0x73: {
>           /* (sz==4): PSLL/PSRA/PSRL mmxreg by imm8 */
> 



		
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