valgrind buffered translated codes in "transtab", and reuse these codes directly if next PC is same as these code.

there is a limit for this design, every code block must have enough instruction information in current code block.

In other ISAs like RISCV Vector [1], current instruction codes depend other state of CSRs like VTYPE/VL,
only PC information is not enough to judge that valgrind should reuse directly buffered code or not.

we need to add cpu state in code translation, and save state into "transtab".

[1] https://github.com/riscv/riscv-v-spec