Created attachment 140356 [details]
arm64: Correct memory barrier position for 8.1-A LSE instructions

Fix guest-to-IR decoding of the Armv8.1-A LSE instructions LD<x>{,A}{,L},
CAS{,A}{,L} and CASP{,A}{,L} which have the memory barrier statement placed at
an incorrect position. For acquire semantics, place the barrier after the IR of
the decoded operation. For release semantics, place the barrier before it.

Note that decoding of the Armv8.0-A instructions LDAXR, STLXR, LDAR and STLR
places the memory barrier statement at the correct position.