Created attachment 131370 [details] add isa 3.1 support for instructiions to guest_ppc_toIR.c This patch contains the third set of patches for the PPC64 ISA 3.1 valgrind support. The set only consists of one Valgrind and one testsuite patch as the are relatively large. The Valgrind patch adds support for the SIMD permute class instructions.
Created attachment 131371 [details] Add 3.1 instruction test suite support
The previous set of patches is in https://bugs.kde.org/show_bug.cgi?id=425232
(In reply to Carl Love from comment #1) > Created attachment 131371 [details] > Add 3.1 instruction test suite support ok to land
(In reply to Carl Love from comment #0) > Created attachment 131370 [details] > add isa 3.1 support for instructiions to guest_ppc_toIR.c ok to land
Created attachment 131912 [details] add isa 3.1 support for instructiions to guest_ppc_toIR.c
Created attachment 131913 [details] Add isa 3.1 instruction test suite support
Updated the valgrind support and testsuite patches to be consistent with upstream and set 2 changes. These patches apply cleanly on top of set 2 patches. The patches have been retested on Power 9 LE and Power 8 BE with no issues.
Created attachment 132165 [details] Add isa 3.1 instruction test suite support Updating the patch to be consistent with the changes to the testsuite patches in set 1.
Patches for part 4 of the ISA 3.1 support are in https://bugs.kde.org/show_bug.cgi?id=427400
Patches committed commit ef76075436a539cc5e71e0113858f2b7849b9ffc (HEAD -> master, origin/master, origin/HEAD) Author: Carl Love <cel@us.ibm.com> Date: Tue Oct 6 11:57:00 2020 -0500 SIMD Permute-Class operations powerpc tests commit 349102dcc790ac2adc88a6b23ee6b371187a2cf0 Author: Carl Love <cel@us.ibm.com> Date: Wed May 13 15:29:51 2020 -0500 ISA 3.1 SIMD Permute-Class Operations Add support for: vxvkq Load VSX Vector Special Value Quadword vextddvlx Vector Extract Double Dword to VSR Left-Indexed vextddvrx Vector Extract Double Dword to VSR Right-Indexed vextdubvlx Vector Extract Double Unsigned Byte to VR Left-Indexed vextdubvrx Vector Extract Double Unsigned Byte to VR Right-Indexed vextduhvlx Vector Extract Double Unsigned Hword to VR Left-Indexed vextduhvrx Vector Extract Double Unsigned Hword to VR Right-Indexed vextduwvlx Vector Extract Double Unsigned Word to VR Left-Indexed vextduwvrx Vector Extract Double Unsigned Word to VR Right-Indexed vinsblx Vector Insert Byte from GPR Left-Indexed vinsbrx Vector Insert Byte from GPR Right-Indexed vinsbvlx Vector Insert Byte from VSR Left-Indexed vinsbvrx Vector Insert Byte from VSR Right-Indexed vinsd Vector Insert Dword from GPR vinsdlx Vector Insert Dword from GPR Left-Indexed vinsdrx Vector Insert Dword from GPR Right-Indexed vinshlx Vector Insert Hword from GPR Left-Indexed vinshrx Vector Insert Hword from GPR Right-Indexed vinshvlx Vector Insert Hword from VSR Left-Indexed vinshvrx Vector Insert Hword from VSR Right-Indexed vinsw Vector Insert Word from GPR vinswlx Vector Insert Word from GPR Left-Indexed vinswrx Vector Insert Word from GPR Right-Indexed vinswvlx Vector Insert Word from VSR Left-Indexed vinswvrx Vector Insert Word from VSR Right-Indexed vsldbi Vector Shift Left Double by Bit Immediate vsrdbi Vector Shift Right Double by Bit Immediate xxblendvb VSX Vector Blend Variable Byte xxblendvd VSX Vector Blend Variable Dword xxblendvh VSX Vector Blend Variable Hword xxblendvw VSX Vector Blend Variable Word xxpermx VSX Vector Permute Extended xxsplti32dx VSX Vector Splat Immediate32 Dword Indexed xxspltidp VSX Vector Splat Immediate DP xxspltiw VSX Vector Splat Immediate Word