Bug 402351 - mips64 libvexmultiarch_test fails on s390x
Summary: mips64 libvexmultiarch_test fails on s390x
Status: RESOLVED FIXED
Alias: None
Product: valgrind
Classification: Developer tools
Component: general (show other bugs)
Version: unspecified
Platform: Other Linux
: NOR normal
Target Milestone: ---
Assignee: Petar Jovanovic
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2018-12-19 16:08 UTC by Mark Wielaard
Modified: 2019-03-14 16:11 UTC (History)
1 user (show)

See Also:
Latest Commit:
Version Fixed In:
Sentry Crash Report:

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Description Mark Wielaard 2018-12-19 16:08:57 UTC 
./none/tests/libvexmultiarch_test 1 0 0 fails on s390x for mips64 because of:

------------------------ Instruction selection ------------------------
(evCheck) lw $9, 804($23); addiu $9, $9, -1; sw $9, 804($23); bgez $t9, nofail; jalr *808($23); nofail:

-- ------ IMark(0x10009B8, 4, 0) ------

-- t9 = ReinterpI64asF64(GET:I64(664))

vex: priv/host_mips_isel.c:4915 (iselInt64Expr): Assertion `!env->mode64' failed.
//// failure exit called by libVEX

The following fixes (or just works around) it:

diff --git a/none/tests/libvex_test.c b/none/tests/libvex_test.c
index a39930f49..ca7eb152a 100644
--- a/none/tests/libvex_test.c
+++ b/none/tests/libvex_test.c
@@ -128,10 +128,10 @@ static UInt arch_hwcaps (VexArch va) {
    case VexArchS390X:  return VEX_HWCAPS_S390X_LDISP;
 #if (__mips_isa_rev>=6)
    case VexArchMIPS32: return VEX_PRID_COMP_MIPS | VEX_MIPS_CPU_ISA_M32R6;
-   case VexArchMIPS64: return VEX_PRID_COMP_MIPS | VEX_MIPS_CPU_ISA_M64R6;
+   case VexArchMIPS64: return VEX_PRID_COMP_MIPS | VEX_MIPS_CPU_ISA_M64R6 | VEX_MIPS_HOST_FR;
 #else
    case VexArchMIPS32: return VEX_PRID_COMP_MIPS;
-   case VexArchMIPS64: return VEX_PRID_COMP_MIPS;
+   case VexArchMIPS64: return VEX_PRID_COMP_MIPS | VEX_MIPS_HOST_FR;
 #endif
    default: failure_exit();
    }
Comment 1 Mark Wielaard 2019-01-06 14:08:22 UTC 
Petar could you take a peek at the above issue and fix/workaround?
Comment 2 Petar Jovanovic 2019-01-10 21:23:18 UTC 
I will take a look at it. Is there a way to reproduce it myself?
I am not seeing any s390 boards on GCC farm unfortunately.
Comment 3 Mark Wielaard 2019-01-10 23:47:23 UTC 
(In reply to Petar Jovanovic from comment #2)
> I will take a look at it. Is there a way to reproduce it myself?
> I am not seeing any s390 boards on GCC farm unfortunately.

I had assumed it would also trigger on ppc64be (s390x is also big endian), but it seems to work fine there. Which might indicate that my patch/logic is wrong.

I'll see if I can get you access to the s390x server that I replicated this on.
Comment 4 Mark Wielaard 2019-01-10 23:57:15 UTC 
For ppc64be this is the output:

//// doing translating guest PPC64(1030) BigEndian 64bits to host MIPS64(1033) BigEndian 64bits

------------------------ Front end ------------------------

	0x103C34C8:                ------ IMark(0x103C34C8, 0, 0) ------
              PUT(1296) = 0x103C34C8:I64
              PUT(1296) = GET:I64(1296); exit-NoDecode

GuestBytes 103C34C8 0   00000000


------------------------ After pre-instr IR optimisation ------------------------

IRSB {
   t0:I64   

   ------ IMark(0x103C34C8, 0, 0) ------
   PUT(1296) = 0x103C34C8:I64; exit-NoDecode
}


------------------------ After instrumentation ------------------------

IRSB {
   t0:I64   

   ------ IMark(0x103C34C8, 0, 0) ------
   PUT(1296) = 0x103C34C8:I64; exit-NoDecode
}


------------------------ After post-instr IR optimisation ------------------------

IRSB {
   t0:I64   

   ------ IMark(0x103C34C8, 0, 0) ------
   PUT(1296) = 0x103C34C8:I64; exit-NoDecode
}


------------------------  After tree-building ------------------------

IRSB {
   t0:I64   

   ------ IMark(0x103C34C8, 0, 0) ------
   PUT(1296) = 0x103C34C8:I64; exit-NoDecode
}


------------------------ Instruction selection ------------------------
(evCheck) lw $9, 8($23); addiu $9, $9, -1; sw $9, 8($23); bgez $t9, nofail; jalr *0($23); nofail:

-- ------ IMark(0x103C34C8, 0, 0) ------

-- PUT(1296) = 0x103C34C8:I64; exit-NoDecode
li %vR1,0x00000000103C34C8
(xAssisted) if (guest_COND.AL) { sw %vR1, 1296($23); move $9, $IRJumpKind_to_TRCVAL(6664); move $9, $disp_assisted; jalr $9; nop; }

  0   (evCheck) lw $9, 8($23); addiu $9, $9, -1; sw $9, 8($23); bgez $t9, nofail; jalr *0($23); nofail:
  1   li %vR1,0x00000000103C34C8
  2   (xAssisted) if (guest_COND.AL) { sw %vR1, 1296($23); move $9, $IRJumpKind_to_TRCVAL(6664); move $9, $disp_assisted; jalr $9; nop; }


------------------------ Register-allocated code ------------------------

  0   (evCheck) lw $9, 8($23); addiu $9, $9, -1; sw $9, 8($23); bgez $t9, nofail; jalr *0($23); nofail:
  1   li $24,0x00000000103C34C8
  2   (xAssisted) if (guest_COND.AL) { sw $24, 1296($23); move $9, $IRJumpKind_to_TRCVAL(6664); move $9, $disp_assisted; jalr $9; nop; }


------------------------ Assembly ------------------------

(evCheck) lw $9, 8($23); addiu $9, $9, -1; sw $9, 8($23); bgez $t9, nofail; jalr *0($23); nofail:
8E E9 00 08 25 29 FF FF AE E9 00 08 05 21 00 03 DE E9 00 00 01 20 F8 09 00 00 00 00 

li $24,0x00000000103C34C8
3C 18 10 3C 37 18 34 C8 

(xAssisted) if (guest_COND.AL) { sw $24, 1296($23); move $9, $IRJumpKind_to_TRCVAL(6664); move $9, $disp_assisted; jalr $9; nop; }
FE F8 05 10 3C 17 00 00 36 F7 00 00 00 17 BC 38 36 F7 00 00 00 17 BC 38 36 F7 00 45 3C 09 00 00 35 29 00 00 00 09 4C 38 35 29 10 3C 00 09 4C 38 35 29 34 98 01 20 F8 09 00 00 00 00 

VexExpansionRatio 0 96   960 :10

For s390x it is:

//// doing translating guest S390X(1031) BigEndian 64bits to host MIPS64(1033) BigEndian 64bits

------------------------ Front end ------------------------

ldgr     %f2,%r11
              ------ IMark(0x1000920, 4, 0) ------
              PUT(96) = ReinterpI64asF64(GET:I64(664))
              PUT(720) = 0x1000924:I64

ldgr     %f0,%r15
              ------ IMark(0x1000924, 4, 0) ------
              PUT(64) = ReinterpI64asF64(GET:I64(696))
              PUT(720) = 0x1000928:I64

lay      %r15,-168(%r15)
              ------ IMark(0x1000928, 6, 0) ------
              t1 = 0xFFFFFFFFFFFFFF58:I64
              t0 = Add64(Add64(t1,GET:I64(696)),0x0:I64)
              PUT(696) = t0
              PUT(720) = 0x100092E:I64

lgr      %r11,%r15
              ------ IMark(0x100092E, 4, 0) ------
              PUT(664) = GET:I64(696)
              PUT(720) = 0x1000932:I64

stg      %r2,160(%r11)
              ------ IMark(0x1000932, 6, 0) ------
              t3 = 0xA0:I64
              t2 = Add64(Add64(t3,GET:I64(664)),0x0:I64)
              STbe(t2) = GET:I64(592)
              PUT(720) = 0x1000938:I64

lg       %r1,160(%r11)
              ------ IMark(0x1000938, 6, 0) ------
              t5 = 0xA0:I64
              t4 = Add64(Add64(t5,GET:I64(664)),0x0:I64)
              PUT(584) = LDbe:I64(t4)
              PUT(720) = 0x100093E:I64

mvhi     0(%r1),1031
              ------ IMark(0x100093E, 6, 0) ------
              t6 = Add64(0x0:I64,GET:I64(584))
              STbe(t6) = 0x407:I32
              PUT(720) = 0x1000944:I64

nopr    
              ------ IMark(0x1000944, 2, 0) ------
              PUT(720) = 0x1000946:I64

lgdr     %r11,%f2
              ------ IMark(0x1000946, 4, 0) ------
              PUT(664) = ReinterpF64asI64(GET:F64(96))
              PUT(720) = 0x100094A:I64

lgdr     %r15,%f0
              ------ IMark(0x100094A, 4, 0) ------
              PUT(696) = ReinterpF64asI64(GET:F64(64))
              PUT(720) = 0x100094E:I64

br       %r14
              ------ IMark(0x100094E, 2, 0) ------
              PUT(720) = GET:I64(688)
              PUT(720) = GET:I64(720); exit-Return

GuestBytes 1000920 48  B3 C1 00 2B B3 C1 00 0F E3 F0 FF 58 FF 71 B9 04 00 BF E3 20 B0 A0 00 24 E3 10 B0 A0 00 04 E5 4C 10 00 04 07 07 00 B3 CD 00 B2 B3 CD 00 F0 07 FE  EC1F5600


------------------------ After pre-instr IR optimisation ------------------------

IRSB {
   t0:I64   t1:I64   t2:I64   t3:I64   t4:I64   t5:I64   t6:I64   t7:I32
   t8:I32   t9:F64   t10:I64   t11:F64   t12:I64   t13:I64   t14:I64   t15:I64
   t16:I64   t17:I64   t18:I64   t19:I64   t20:I64   t21:I64   t22:I64   t23:I64
   t24:I64   t25:I64   t26:I64   t27:I64   t28:F64   t29:I64   t30:F64   t31:I64
   t32:I64   

   ------ IMark(0x1000920, 4, 0) ------
   t10 = GET:I64(664)
   t9 = ReinterpI64asF64(t10)
   PUT(96) = t9
   ------ IMark(0x1000924, 4, 0) ------
   t12 = GET:I64(696)
   t11 = ReinterpI64asF64(t12)
   PUT(64) = t11
   ------ IMark(0x1000928, 6, 0) ------
   t14 = Add64(0xFFFFFFFFFFFFFF58:I64,t12)
   PUT(696) = t14
   ------ IMark(0x100092E, 4, 0) ------
   PUT(664) = t14
   PUT(720) = 0x1000932:I64
   ------ IMark(0x1000932, 6, 0) ------
   t18 = Add64(0xA0:I64,t14)
   t20 = GET:I64(592)
   STbe(t18) = t20
   PUT(720) = 0x1000938:I64
   ------ IMark(0x1000938, 6, 0) ------
   t22 = t18
   t24 = LDbe:I64(t22)
   PUT(584) = t24
   PUT(720) = 0x100093E:I64
   ------ IMark(0x100093E, 6, 0) ------
   STbe(t24) = 0x407:I32
   ------ IMark(0x1000944, 2, 0) ------
   ------ IMark(0x1000946, 4, 0) ------
   t27 = ReinterpF64asI64(t9)
   PUT(664) = t27
   ------ IMark(0x100094A, 4, 0) ------
   t29 = ReinterpF64asI64(t11)
   PUT(696) = t29
   ------ IMark(0x100094E, 2, 0) ------
   t31 = GET:I64(688)
   PUT(720) = t31; exit-Return
}


------------------------ After instrumentation ------------------------

IRSB {
   t0:I64   t1:I64   t2:I64   t3:I64   t4:I64   t5:I64   t6:I64   t7:I32
   t8:I32   t9:F64   t10:I64   t11:F64   t12:I64   t13:I64   t14:I64   t15:I64
   t16:I64   t17:I64   t18:I64   t19:I64   t20:I64   t21:I64   t22:I64   t23:I64
   t24:I64   t25:I64   t26:I64   t27:I64   t28:F64   t29:I64   t30:F64   t31:I64
   t32:I64   

   ------ IMark(0x1000920, 4, 0) ------
   t10 = GET:I64(664)
   t9 = ReinterpI64asF64(t10)
   PUT(96) = t9
   ------ IMark(0x1000924, 4, 0) ------
   t12 = GET:I64(696)
   t11 = ReinterpI64asF64(t12)
   PUT(64) = t11
   ------ IMark(0x1000928, 6, 0) ------
   t14 = Add64(0xFFFFFFFFFFFFFF58:I64,t12)
   PUT(696) = t14
   ------ IMark(0x100092E, 4, 0) ------
   PUT(664) = t14
   PUT(720) = 0x1000932:I64
   ------ IMark(0x1000932, 6, 0) ------
   t18 = Add64(0xA0:I64,t14)
   t20 = GET:I64(592)
   STbe(t18) = t20
   PUT(720) = 0x1000938:I64
   ------ IMark(0x1000938, 6, 0) ------
   t22 = t18
   t24 = LDbe:I64(t22)
   PUT(584) = t24
   PUT(720) = 0x100093E:I64
   ------ IMark(0x100093E, 6, 0) ------
   STbe(t24) = 0x407:I32
   ------ IMark(0x1000944, 2, 0) ------
   ------ IMark(0x1000946, 4, 0) ------
   t27 = ReinterpF64asI64(t9)
   PUT(664) = t27
   ------ IMark(0x100094A, 4, 0) ------
   t29 = ReinterpF64asI64(t11)
   PUT(696) = t29
   ------ IMark(0x100094E, 2, 0) ------
   t31 = GET:I64(688)
   PUT(720) = t31; exit-Return
}


------------------------ After post-instr IR optimisation ------------------------

IRSB {
   t0:I64   t1:I64   t2:I64   t3:I64   t4:I64   t5:I64   t6:I64   t7:I32
   t8:I32   t9:F64   t10:I64   t11:F64   t12:I64   t13:I64   t14:I64   t15:I64
   t16:I64   t17:I64   t18:I64   t19:I64   t20:I64   t21:I64   t22:I64   t23:I64
   t24:I64   t25:I64   t26:I64   t27:I64   t28:F64   t29:I64   t30:F64   t31:I64
   t32:I64   

   ------ IMark(0x1000920, 4, 0) ------
   t10 = GET:I64(664)
   t9 = ReinterpI64asF64(t10)
   PUT(96) = t9
   ------ IMark(0x1000924, 4, 0) ------
   t12 = GET:I64(696)
   t11 = ReinterpI64asF64(t12)
   PUT(64) = t11
   ------ IMark(0x1000928, 6, 0) ------
   t14 = Add64(0xFFFFFFFFFFFFFF58:I64,t12)
   PUT(696) = t14
   ------ IMark(0x100092E, 4, 0) ------
   PUT(664) = t14
   PUT(720) = 0x1000932:I64
   ------ IMark(0x1000932, 6, 0) ------
   t18 = Add64(0xA0:I64,t14)
   t20 = GET:I64(592)
   STbe(t18) = t20
   PUT(720) = 0x1000938:I64
   ------ IMark(0x1000938, 6, 0) ------
   t22 = t18
   t24 = LDbe:I64(t22)
   PUT(584) = t24
   PUT(720) = 0x100093E:I64
   ------ IMark(0x100093E, 6, 0) ------
   STbe(t24) = 0x407:I32
   ------ IMark(0x1000944, 2, 0) ------
   ------ IMark(0x1000946, 4, 0) ------
   t27 = ReinterpF64asI64(t9)
   PUT(664) = t27
   ------ IMark(0x100094A, 4, 0) ------
   t29 = ReinterpF64asI64(t11)
   PUT(696) = t29
   ------ IMark(0x100094E, 2, 0) ------
   t31 = GET:I64(688)
   PUT(720) = t31; exit-Return
}


------------------------  After tree-building ------------------------

IRSB {
   t0:I64   t1:I64   t2:I64   t3:I64   t4:I64   t5:I64   t6:I64   t7:I32
   t8:I32   t9:F64   t10:I64   t11:F64   t12:I64   t13:I64   t14:I64   t15:I64
   t16:I64   t17:I64   t18:I64   t19:I64   t20:I64   t21:I64   t22:I64   t23:I64
   t24:I64   t25:I64   t26:I64   t27:I64   t28:F64   t29:I64   t30:F64   t31:I64
   t32:I64   

   ------ IMark(0x1000920, 4, 0) ------
   t9 = ReinterpI64asF64(GET:I64(664))
   PUT(96) = t9
   ------ IMark(0x1000924, 4, 0) ------
   t12 = GET:I64(696)
   t11 = ReinterpI64asF64(t12)
   PUT(64) = t11
   ------ IMark(0x1000928, 6, 0) ------
   t14 = Add64(0xFFFFFFFFFFFFFF58:I64,t12)
   PUT(696) = t14
   ------ IMark(0x100092E, 4, 0) ------
   PUT(664) = t14
   PUT(720) = 0x1000932:I64
   ------ IMark(0x1000932, 6, 0) ------
   t18 = Add64(0xA0:I64,t14)
   STbe(t18) = GET:I64(592)
   PUT(720) = 0x1000938:I64
   ------ IMark(0x1000938, 6, 0) ------
   t24 = LDbe:I64(t18)
   PUT(584) = t24
   PUT(720) = 0x100093E:I64
   ------ IMark(0x100093E, 6, 0) ------
   STbe(t24) = 0x407:I32
   ------ IMark(0x1000944, 2, 0) ------
   ------ IMark(0x1000946, 4, 0) ------
   PUT(664) = ReinterpF64asI64(t9)
   ------ IMark(0x100094A, 4, 0) ------
   PUT(696) = ReinterpF64asI64(t11)
   ------ IMark(0x100094E, 2, 0) ------
   PUT(720) = GET:I64(688); exit-Return
}


------------------------ Instruction selection ------------------------
(evCheck) lw $9, 804($23); addiu $9, $9, -1; sw $9, 804($23); bgez $t9, nofail; jalr *808($23); nofail:

-- ------ IMark(0x1000920, 4, 0) ------

-- t9 = ReinterpI64asF64(GET:I64(664))

vex: priv/host_mips_isel.c:4915 (iselInt64Expr): Assertion `!env->mode64' failed.
Comment 5 Julian Seward 2019-03-10 09:42:39 UTC 
> t9 = ReinterpI64asF64(GET:I64(664))
> vex: priv/host_mips_isel.c:4915 (iselInt64Expr): Assertion `!env->mode64' 
> failed.

Either (1) there is some 32-vs-64-bit guest-vs-host confusion here, or (2)
there is no confusion, and instead this is a mips32 instruction selector
problem.

For (2) the test requires iselInt64Expr to select 32-bit instructions for
GET:I64(664), which should be two 32-bit loads into two registers.
Comment 6 Petar Jovanovic 2019-03-14 15:53:02 UTC 
This problem is triggered when VEX is configured for MIPS64 w/ 32-bit FPUs. Since this can happen only in artificial cases, I will go with adjusting the test itself.
Comment 7 Petar Jovanovic 2019-03-14 16:11:07 UTC 
Fixed with
https://sourceware.org/git/?p=valgrind.git;a=commit;h=cd20c8ca5815f0abf9d1bdb47888753bdb5c5738

Sorry for a delay in taking a look at this.