Bug 379925 - PPC64, mtffs does not set the FPCC and C bits in the FPSCR register
Summary: PPC64, mtffs does not set the FPCC and C bits in the FPSCR register
Status: CLOSED FIXED
Alias: None
Product: valgrind
Classification: Developer tools
Component: vex (other bugs)
Version First Reported In: 3.10 SVN
Platform: Other Linux
: NOR normal
Target Milestone: ---
Assignee: Julian Seward
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2017-05-16 22:25 UTC by Carl Love
Modified: 2017-05-18 15:06 UTC (History)
0 users

See Also:
Latest Commit:
Version Fixed/Implemented In:
Sentry Crash Report:

Attachments
patch for the mffs and additional issues (7.92 KB, patch)
2017-05-17 20:07 UTC, Carl Love 		Details
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Description Carl Love 2017-05-16 22:25:27 UTC 
mtffs does not set the FPCC and C bits in the FPSCR register.  The putGST_masked() and getGST_masked() are not correctly handling accesses to the FPSCR
Comment 1 Carl Love 2017-05-17 20:07:47 UTC 
Created attachment 105610 [details]
patch for the mffs and additional issues


Some additional fixes:

- Fix mffs instruction, FPSCR, C_FPCC field access is not working correctly. 
- Fix xscmpexpdp again still had a bug.
- Remove duplicate tests from test_isa_3_0.c
- Comment out he tests for the new ISA 3.0B instructions.  There seem to be some issues between the simulator and early HW that need to be sorted out.

Update the expected output again using the ISA 3.0 HW output instead of the simulator output.  Patch with updated expected output not included in patch
Comment 2 Carl Love 2017-05-17 20:12:26 UTC 
Committed patch
Vex commit 3375,  Valgrind commit 16396
Comment 3 Carl Love 2017-05-18 15:06:52 UTC 
No issues seen in the nightly regression test.  Closing.