When running a program under Valgrind on a zEC12 or z13 whose glibc has lock elision enabled, the glibc infers from HWCAP that the prerequisites for lock elision are met. Then it may use TBEGIN, which is not implemented by Valgrind. The failure can be reproduced with drd/tests/atomic_var from the Valgrind test suite: vex s390->IR: unimplemented insn: E560 0000 FF0C valgrind: Unrecognised instruction at address 0x......... at 0x........: (within libpthread-?.?.so) by 0x........: ??? A similar problem may occur with the upcoming glibc release 2.23, since it will optimize various string functions with vector instructions on z13 when available. See: https://sourceware.org/ml/libc-alpha/2015-07/msg00077.html One way of fixing this would be to implement the missing instructions in Valgrind: the transactional-execution- and all vector instructions. Another way is to mask off unsupported/unknown hardware features from HWCAP. The latter approach should also help for any future unsupported hardware features. Reproducible: Always
Created attachment 94888 [details] Mask off unsupported features from HWCAP
Thanks for the patch. Applied as r15702.