Memcheck checks PPC32 cache size using dcbz instruction.
On MPC8xx, cache lines are 16 bytes
Memcheck has an assert check (several places) which only accepts 32, 64 and 128

Reproducible: Always

Steps to Reproduce:
launch valgrind on MPC8xx processor
Actual Results:  

valgrind: m_machine.c:479 (find_ppc_dcbz_sz): Assertion 'dcbz_szB == 32 || dcbz_szB == 64 || dcbz_szB == 128' failed.
==3767==    at 0x38033AB8: ??? (in /usr/local/lib/valgrind/memcheck-ppc32-linux)

sched status:
  running_tid=0



Expected Results:  
No error

diff -ru valgrind-3.8.1.org/VEX/priv/guest_ppc_toIR.c valgrind-3.8.1/VEX/priv/guest_ppc_toIR.c
--- valgrind-3.8.1.org/VEX/priv/guest_ppc_toIR.c	2012-08-17 09:00:00.000000000 +0200
+++ valgrind-3.8.1/VEX/priv/guest_ppc_toIR.c	2012-10-04 04:36:37.000000000 +0200
@@ -6675,7 +6675,7 @@
    }
 
    /* stay sane .. */
-   vassert(lineszB == 32 || lineszB == 64 || lineszB == 128);
+   vassert(lineszB == 16 || lineszB == 32 || lineszB == 64 || lineszB == 128);
    
    switch (opc2) {
 //zz    case 0x2F6: // dcba (Data Cache Block Allocate, PPC32 p380)
diff -ru valgrind-3.8.1.org/coregrind/m_libcproc.c valgrind-3.8.1/coregrind/m_libcproc.c
--- valgrind-3.8.1.org/coregrind/m_libcproc.c	2012-08-17 08:59:57.000000000 +0200
+++ valgrind-3.8.1/coregrind/m_libcproc.c	2012-10-04 04:33:17.000000000 +0200
@@ -738,7 +738,7 @@
    cls = vai.ppc_cache_line_szB;
 
    /* Stay sane .. */
-   vg_assert(cls == 32 || cls == 64 || cls == 128);
+   vg_assert(cls == 16 || cls == 32 || cls == 64 || cls == 128);
 
    startaddr &= ~(cls - 1);
    for (addr = startaddr; addr < endaddr; addr += cls) {
diff -ru valgrind-3.8.1.org/coregrind/m_machine.c valgrind-3.8.1/coregrind/m_machine.c
--- valgrind-3.8.1.org/coregrind/m_machine.c	2012-08-17 08:59:57.000000000 +0200
+++ valgrind-3.8.1/coregrind/m_machine.c	2012-10-04 04:33:53.000000000 +0200
@@ -476,7 +476,7 @@
       if (!test_block[i])
          ++dcbz_szB;
    }
-   vg_assert(dcbz_szB == 32 || dcbz_szB == 64 || dcbz_szB == 128);
+   vg_assert(dcbz_szB == 16 || dcbz_szB == 32 || dcbz_szB == 64 || dcbz_szB == 128);
 
    /* dcbzl clears 128B on G5/PPC970, and usually 32B on other platforms */
    if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
@@ -494,7 +494,7 @@
          if (!test_block[i])
             ++dcbzl_szB;
       }
-      vg_assert(dcbzl_szB == 32 || dcbzl_szB == 64 || dcbzl_szB == 128);
+      vg_assert(dcbzl_szB == 16 || dcbzl_szB == 32 || dcbzl_szB == 64 || dcbzl_szB == 128);
    }
 
    arch_info->ppc_dcbz_szB  = dcbz_szB;
@@ -1380,7 +1382,7 @@
    vg_assert(vai.ppc_cache_line_szB == 0
              || vai.ppc_cache_line_szB == szB);
 
-   vg_assert(szB == 32 || szB == 64 || szB == 128);
+   vg_assert(szB == 16 || szB == 32 || szB == 64 || szB == 128);
    vai.ppc_cache_line_szB = szB;
 }
 #endif
@@ -1398,7 +1400,7 @@
    vg_assert(vai.ppc_cache_line_szB == 0
              || vai.ppc_cache_line_szB == szB);
 
-   vg_assert(szB == 32 || szB == 64 || szB == 128);
+   vg_assert(szB == 16 || szB == 32 || szB == 64 || szB == 128);
    vai.ppc_cache_line_szB = szB;
 }
 #endif