Consider this IR: STbe(0x4040070:I64) = ReinterpD64asI64(ShlD64(ReinterpI64asD64(LDbe:I64(0x40400C0:I64)),LDbe:I8(0x4040110:I64))) as generated by the V-bit tester. When run through valgrind it will assert like so: vex: priv/host_ppc_defs.c:3158 (mkFormZ22): Assertion `constant < 0x40' failed. The reason is that in host_ppc_isel.c around line 3970 the shift amount for Iop_ShlD64 is compiled into a register or an immediate value (iselWordExpr_RI). Then a PPCInstr_DfpShift insn is created. When code is later generated for Pin_DfpShift (host_ppc_defs.c line 2460) it is assumed that the shift amount is an immediate value: shift = i->Pin.DfpShift.shift->Pri.Imm; And because that's not the case when compiling the above IR we will run into an assert in mkFormZ22.
Above analysis also applies to ShlD128 / ShrD128. Those ops have the same problem.
Florian, nice catch. Does the 32 bit ppc insn selection also fail?
The shift amount for the ppc DFP shift insn is given in an immediate field. Therefore, the insn selector cannot find a cover for the IR in comment #1. The vbit-tester needs to be adjusted to deal with this. I'm leaving this bug open and assign it to myself.
Added vassert for DFP shift value to make sure shift value is an immediate value. Change made to file VEX/priv/host_ppc_isel.c VEX committed revision 2512
Fixed in VEX r2529 and valgrind r12969. Testing of Iop_ShlD64 etc is now enabled for the vbit tester on ppc platforms.
The issue was fixed. No additional issues have been found related to this bug. Closing.