| Summary: | ppc64: code generation for ShlD64 / ShrD64 asserts | ||
|---|---|---|---|
| Product: | [Developer tools] valgrind | Reporter: | Florian Krohm <flo2030> |
| Component: | vex | Assignee: | Florian Krohm <flo2030> |
| Status: | CLOSED FIXED | ||
| Severity: | normal | CC: | cel |
| Priority: | NOR | ||
| Version First Reported In: | unspecified | ||
| Target Milestone: | --- | ||
| Platform: | unspecified | ||
| OS: | Linux | ||
| Latest Commit: | Version Fixed/Implemented In: | ||
| Sentry Crash Report: | |||
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Description
Florian Krohm
2012-08-28 20:47:47 UTC
Above analysis also applies to ShlD128 / ShrD128. Those ops have the same problem. Florian, nice catch. Does the 32 bit ppc insn selection also fail? The shift amount for the ppc DFP shift insn is given in an immediate field. Therefore, the insn selector cannot find a cover for the IR in comment #1. The vbit-tester needs to be adjusted to deal with this. I'm leaving this bug open and assign it to myself. Added vassert for DFP shift value to make sure shift value is an immediate value. Change made to file VEX/priv/host_ppc_isel.c VEX committed revision 2512 Fixed in VEX r2529 and valgrind r12969. Testing of Iop_ShlD64 etc is now enabled for the vbit tester on ppc platforms. The issue was fixed. No additional issues have been found related to this bug. Closing. |