Bug 468979

Summary:	Add support for RISC-V vector instructions
Product:	[Developer tools] valgrind	Reporter:	JojoR <rjiejie>
Component:	vex	Assignee:	Julian Seward <jseward>
Status:	REPORTED ---
Severity:	normal	CC:	jlp, pjfloyd
Priority:	NOR
Version First Reported In:	unspecified
Target Milestone:	---
Platform:	Other
OS:	Linux
Latest Commit:		Version Fixed/Implemented In:
Sentry Crash Report:

Description JojoR 2023-04-26 01:50:59 UTC

We consider to add RVV/Vector [1] feature in valgrind, there are some challenges.
RVV like ARM's SVE [2] programming model, it's scalable/VLA, that means the vector length is agnostic.
ARM's SVE is not supported in valgrind :(

See more details from RFC [3]

[1] https://github.com/riscv/riscv-v-spec
[2] https://community.arm.com/arm-research/b/articles/posts/the-arm-scalable-vector-extension-sve
[3] https://sourceforge.net/p/valgrind/mailman/valgrind-developers/thread/84b7a55c-1868-ca14-2626-ffb88925741a%40linux.alibaba.com/#msg37834524

Comment 1 JojoR 2023-08-30 09:45:46 UTC

Hi,

We are glad to open source RVV implementation here:

https://github.com/rjiejie/valgrind-riscv64

4 kinds extra ISAs were added in this repo:

RV64Zfh : Half-precision floating-point
RV64Xthead [1] : T-HEAD vendor extension for RV64G
RV64V0p7 [2] : Vector 0.7.1
RV64V [3] : Vector 1.0

[1] https://github.com/T-head-Semi/thead-extension-spec
[2] https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1
[3] https://github.com/riscv/riscv-v-spec/releases/tag/v1.0