| Summary: | Complete arm64 FADDP v8.2 instruction support started in 413547 | ||
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| Product: | [Developer tools] valgrind | Reporter: | ahashmi <assad.hashmi> |
| Component: | vex | Assignee: | ahashmi <assad.hashmi> |
| Status: | RESOLVED FIXED | ||
| Severity: | normal | CC: | jseward |
| Priority: | NOR | ||
| Version: | unspecified | ||
| Target Milestone: | --- | ||
| Platform: | Other | ||
| OS: | Linux | ||
| Latest Commit: | Version Fixed In: | ||
| Sentry Crash Report: | |||
| Attachments: |
arm64 v8.2 faddp instruction support
Patch completes addition of arm64 v8.2 faddp instructions. Patch completes addition of arm64 v8.2 faddp instructions. |
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Description
ahashmi
2021-01-13 17:45:20 UTC
Created attachment 134815 [details]
arm64 v8.2 faddp instruction support
Patch completes addition of arm64 v8.2 faddp instructions.
Created attachment 134852 [details]
Patch completes addition of arm64 v8.2 faddp instructions.
(In reply to ahashmi from comment #2) > Created attachment 134852 [details] > Patch completes addition of arm64 v8.2 faddp instructions. Looks good to me; a couple of small queries, but basically is landable. --- The cases are distinguished as follows: isD == True, bitQ == 1 => 2d isD == False, bitQ == 1 => 4s isD == False, bitQ == 0 => 2s + isH == True, bitQ == 0 => 4h + isH == False, bitQ == 1 => 8h Is this comment out of date? The function it applies to takes an ARM64VecESize now, not isH / isD. --- + if (1) test_faddp_4h_00_00_00(TyH); The tests where the three register numbers are the same .. are they of any value? In particular, they won't expose mixups where the wrong register number is used in decode. Those cases are covered by the _N_N+1_N+2 variants afaics. Is there some other reason to keep the N_N_N variants? (In reply to Julian Seward from comment #3) > The cases are distinguished as follows: > isD == True, bitQ == 1 => 2d > isD == False, bitQ == 1 => 4s > isD == False, bitQ == 0 => 2s > + isH == True, bitQ == 0 => 4h > + isH == False, bitQ == 1 => 8h > > Is this comment out of date? The function it applies to takes an > ARM64VecESize now, > not isH / isD. Ah yes! It is out-of-date. I'll remove. > + if (1) test_faddp_4h_00_00_00(TyH); > > The tests where the three register numbers are the same .. are they of any > value? In particular, they won't expose mixups where the wrong register > number is used in decode. Those cases are covered by the _N_N+1_N+2 variants > afaics. Is there some other reason to keep the N_N_N variants? The reason for the N_N_N variants is that they may flush out bugs to do with temporaries in IR. That's my simple minded motivation. If such bugs are not possible I can remove. Created attachment 134859 [details]
Patch completes addition of arm64 v8.2 faddp instructions.
Changes after review. Removed redundant;
- comment in math_REARRANGE_FOR_FLOATING_PAIRWISE()
- N_N_N test case variants in fp_and_simd_v82.c
Landed, 8fa9e36f7c269563feebbf41a7a658bc7879ad39. |