Bug 430117

Summary:	Implement guest Arm64/AArch64 feature detection support for v8 instructions
Product:	[Developer tools] valgrind	Reporter:	ahashmi <assad.hashmi>
Component:	vex	Assignee:	Julian Seward <jseward>
Status:	RESOLVED FIXED
Severity:	normal	CC:	pjfloyd
Priority:	NOR
Version:	unspecified
Target Milestone:	---
Platform:	Other
OS:	Linux
Latest Commit:		Version Fixed In:
Sentry Crash Report:

Description ahashmi 2020-12-07 18:01:48 UTC

SUMMARY
The bug https://bugs.kde.org/show_bug.cgi?id=414268 added host AArch64 feature detection and decoding for v8.x.

However, Valgrind must provide a view of v8.x instructions supported by Valgrind to the guest which will not be the same as those supported by the host, until they have been implemented in Valgrind.

ADDITIONAL INFORMATION
A helper function needs to be implemented which provides a filtered view to the guest of a set of instructions implemented by Valgrind.

This is not the same as the set of instructions supported by the host which Valgrind reads in order to decode instructions which may or may not be supported by Valgrind.

When instructions are decoded, this helper function is planted in the IR to provide the guest with the filtered view of what Valgrind wants the guest to think are the instructions supported by the host.

As an existing example, see the x86 implementation of populating guest state with SSE1 support: x86g_dirtyhelper_CPUID_sse1(). This sets VexGuestX86State with SSE1 features supported by Valgrind. A pointer to the function is planted in IR by unsafeIRDirty_0_N() when SSE1 instructions are decoded.

Comment 1 Paul Floyd 2024-05-12 05:36:29 UTC

I think that this was mostly resolved with 9ecbb9037b596babf69745f9e212c80b2cef4174 [Bug 392146 - aarch64: unhandled instruction 0xD5380001 (MRS rT, midr_el1)]

Specifically, MRS ID_AA64ISAR0_EL1 end similar registers are now handled, with filtering in the dirty helper to filter out unsupported features.