Bug 417572

Summary:	vex amd64->IR: unhandled instruction bytes: 0xC5 0x79 0xD6 0xED 0xC5 0xF9 0x51
Product:	[Developer tools] valgrind	Reporter:	Arnaud Desitter <arnaud.desitter>
Component:	vex	Assignee:	Julian Seward <jseward>
Status:	REOPENED ---
Severity:	normal	CC:	masterchi23, tom
Priority:	NOR
Version:	3.21 GIT
Target Milestone:	---
Platform:	Ubuntu
OS:	Linux
Latest Commit:		Version Fixed In:

Description Arnaud Desitter 2020-02-13 15:30:58 UTC

SUMMARY

vex amd64->IR: unhandled instruction bytes: 0xC5 0x79 0xD6 0xED 0xC5 0xF9 0x51 0xF5 0xC5 0xF3
vex amd64->IR:   REX=0 REX.W=0 REX.R=1 REX.X=0 REX.B=0
vex amd64->IR:   VEX=1 VEX.L=0 VEX.nVVVV=0x0 ESC=0F
vex amd64->IR:   PFX.66=1 PFX.F2=0 PFX.F3=0
==31642== valgrind: Unrecognised instruction at address 0x140630d6.
==31642==    at 0x140630D6: _mm_set_sd (emmintrin.h:68)
==31642==    by 0x140630D6: sqrt<double> (MathFunctions.h:554)
==31642==    by 0x140630D6: normalized (Dot.h:131)

This is some C++ code using Eigen and built with gcc 9.2 "-O3 -mavx". I failed to find a small reproducer.

Comment 1 masterchi23 2022-12-09 08:54:55 UTC

I have almost the exact same error:
vex amd64->IR: unhandled instruction bytes: 0xC5 0x79 0xD6 0xD3 0xC5 0x79 0xD6 0xE0 0xC5 0x7A
vex amd64->IR:   REX=0 REX.W=0 REX.R=1 REX.X=0 REX.B=0
vex amd64->IR:   VEX=1 VEX.L=0 VEX.nVVVV=0x0 ESC=0F
vex amd64->IR:   PFX.66=1 PFX.F2=0 PFX.F3=0
==24742== valgrind: Unrecognised instruction at address 0x4fef051.

version: valgrind-3.21.0.GIT

Comment 2 masterchi23 2023-05-09 08:50:58 UTC

In latest git this is still the same problem. It is coming from a common _mm_loadl_epi64 intrinsic. 
I compiled the source with both g++ 11.3.0 and 12.1.0, same results. When compiling with -O0 this does not occur.

vex amd64->IR: unhandled instruction bytes: 0xC5 0x79 0xD6 0xD3 0xC5 0x79 0xD6 0xE0 0xC5 0x7A
vex amd64->IR:   REX=0 REX.W=0 REX.R=1 REX.X=0 REX.B=0
vex amd64->IR:   VEX=1 VEX.L=0 VEX.nVVVV=0x0 ESC=0F
vex amd64->IR:   PFX.66=1 PFX.F2=0 PFX.F3=0
==14165== valgrind: Unrecognised instruction at address 0x5cf15c1.
==14165==    at 0x5CF15C1: _mm_set_epi64x (emmintrin.h:592)
==14165==    by 0x5CF15C1: _mm_set_epi64 (emmintrin.h:598)
==14165==    by 0x5CF15C1: _mm_loadl_epi64 (emmintrin.h:709)

Comment 3 Tom Hughes 2023-05-09 09:02:28 UTC

That is an AVX512 instruction, or at least uses EVEX encoding, which means it is dependent on AVX512 support being added.

Until then you will need to compile to target an architecture that does not support AVX512.

*** This bug has been marked as a duplicate of bug 383010 ***

Comment 4 Tom Hughes 2023-05-09 09:03:40 UTC

Scratch that I'm talking nonsense - that is VEX encoding.

Comment 5 Tom Hughes 2023-05-09 09:07:57 UTC

I believe the instruction is:

VEX.128.66.0F.WIG D6 /r
VMOVQ xmm1/m64, xmm2

Move quadword from xmm2 register to xmm1/m64.