Bug 384526

VEX register allocator v2 has a clever optimization which reduces a number of spill instructions generated.

Let's have the following vcode:
...
 97: orq %vR250,%vR570
 98: movslq %vR570d,%vR569
 99: movq %vR329,%vR571
100: orq %vR569,%vR571
101: callnz[0,RLPri_None]

and the following vreg ranges:
%vR250: [ 12, 214)
%vR329: [ 72, 162)
%vR569: [ 98, 101)
%vR570: [ 95,  99)
%vR571: [ 99, 101)

Now reg. alloc. v2 produces the following rcode:
 82   orq %rbx,%r8
 83   movslq %r8d,%rdi
 84   movq 0xB28(%rbp),%r8
 85   movq %r8,%rsi
 86   orq %rdi,%rsi
 87   movq %r9,0xAE0(%rbp)
 88   callnz[0,RLPri_None] 0x5805E8E0

However current regalloc v3 produces more rcode:
 82   orq %rbx,%r8
 83   movslq %r8d,%rdi
 84   movq 0xB28(%rbp),%r8
 85   movq %r8,%rsi
 86   orq %rdi,%rsi
 87   movq %r9,0xAE0(%rbp)
 88   movq %r8,0xB28(%rbp)
 89   callnz[0,RLPri_None] 0x5805E8E0

It can be seen that spilling %r8 (instruction #88) is useless because its value is still equal to that one in the spill slot.