Summary: | POWER AvSplat ought to load destination vector register with 16/16 bytes stored prior. | ||
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Product: | [Developer tools] valgrind | Reporter: | Anmol P. Paralkar <paralkar> |
Component: | vex | Assignee: | Julian Seward <jseward> |
Status: | CLOSED FIXED | ||
Severity: | normal | CC: | cel, florian, maynardj, paralkar, philippe.waroquiers |
Priority: | NOR | ||
Version: | unspecified | ||
Target Milestone: | --- | ||
Platform: | Other | ||
OS: | Linux | ||
Latest Commit: | Version Fixed In: | ||
Attachments: |
Further description and analysis.
Patch to fix the problem. |
Description
Anmol P. Paralkar
2014-09-18 16:17:14 UTC
Created attachment 88742 [details]
Further description and analysis.
Please see sections:
VSPLTB_MISTRANSLATION
WHY_IS_THIS_NOT_A_VG-3.9.0_BUG
FIX
Created attachment 88743 [details]
Patch to fix the problem.
Testing information: Regression tested on a IBM POWER7: processor : 0-31 cpu : POWER7 (architected), altivec supported clock : 3000.000000MHz revision : 2.1 (pvr 003f 0201) timebase : 512000000 platform : pSeries model : IBM,8202-E4B machine : CHRP IBM,8202-E4B running linux 3.1.5-6.fc16.ppc64 with valgrind: 14550, VEX: 2953 PS: none/tests/ppc64/jm-insns.c already includes unit-tests for vsplt[bwh]. If there is a way to grep for patterns after the internal instruction selection phase, (like in GCC's DejaGNU tests) please do let me know and I'll be happy to write a test that checks that an lvx is generated prior to the vsr in the code for the vsplt's. Thanks. The issue was confirmed as a bug. The patch was applied and committed. The VEX commit id is 2960. Thanks for finding this bug. (In reply to Carl Love from comment #4) > The issue was confirmed as a bug. The patch was applied and committed. The > VEX commit id is 2960. If bug is completely fixed, then an entry should be added in NEWS Updated the News file with the fixed bug description. vex commit 14589. Closing the bug. |