| Summary: | [PATCH] POWER5+/POWER6 instructions: frip, frin, friz, frim, cmpb, mftgpr, mffgpr | ||
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| Product: | [Developer tools] valgrind | Reporter: | Pete Eberlein <eberlein> |
| Component: | general | Assignee: | Julian Seward <jseward> |
| Status: | REPORTED --- | ||
| Severity: | wishlist | CC: | will_schmidt |
| Priority: | NOR | ||
| Version First Reported In: | unspecified | ||
| Target Milestone: | --- | ||
| Platform: | Compiled Sources | ||
| OS: | Linux | ||
| Latest Commit: | Version Fixed/Implemented In: | ||
| Sentry Crash Report: | |||
| Attachments: |
POWER5+/POWER6 instructions patch
POWER5+/POWER6 instructions patch for 3.2.3 |
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Description
Pete Eberlein
2007-05-16 02:56:34 UTC
Created attachment 20579 [details]
POWER5+/POWER6 instructions patch
Created attachment 20984 [details]
POWER5+/POWER6 instructions patch for 3.2.3
Added an optional patch that can be applied to Valgrind 3.2.3 release
Hmm, I noticed one thing which I think is wrong. There should be no difference between 32bit mode and 64bit mode for those instructions really. They are never implemented on a 32bit processor, only a 64bit one. -- Pinski Looks like the associated patches for this bug went into valgrind as "r11338 | sewardj | 2010-09-03 18:49:33 -0500 (Fri, 03 Sep 2010) | 4 lines".. should be able to mark this one out as "resolved". |